Electronics Forum | Mon Jul 26 18:01:30 EDT 1999 | Earl Moon
| Presently protos of micro-bgas (80i/o) pitch .030/.031 | 12BGA per assembly | | The board is a (.062, 4 layers) FR-4 using Dry film | Pads .014inch | Vias within footprint .020inch | Vias to be filled by bottom side(solder side) only .030in dia. F
Electronics Forum | Fri Aug 22 09:41:49 EDT 2003 | davef
Mantis: Kenny reflows paste on [wave solders] all via, not just the test via, to plug the via and provide for a pressure seal between the board and the test fixture. Beyond that, since solder is softer than copper [and fills the hole better], solde
Electronics Forum | Mon Jul 26 18:05:18 EDT 1999 | ScottM
| Presently protos of micro-bgas (80i/o) pitch .030/.031 | 12BGA per assembly | | The board is a (.062, 4 layers) FR-4 using Dry film | Pads .014inch | Vias within footprint .020inch | Vias to be filled by bottom side(solder side) only .030in dia. F
Electronics Forum | Fri Jun 11 03:50:39 EDT 2004 | Scott B
We currently have an issue with via's in pads which we have been living with for some time. The problem has now escalated with the need to increase the via hole size to achieve PCB fabricators aspect ratio's. We are now not only experiencing solder d
Electronics Forum | Tue Mar 22 20:33:24 EST 2005 | davef
Q1. What are you guys doing for filled/tented/plugged vias on the BGA site? A2. 2221A, 4.5.1 tells you the vias have to be tented on both sides. Q2. What type of issues can this cause if using no filled/tented/plugged vias on the BGA site? A2. BGA
Electronics Forum | Tue Aug 23 13:10:29 EDT 2005 | davef
We've never heard of this [but all of our gold is electroless, not electrolytic]. If the delamination is caused by the electroylic gold finishing and the via plug process during fabrication, something is wrong. Either your supplier: * Is goofy ...
Electronics Forum | Wed Dec 10 16:00:07 EST 2008 | cisridn
Just to update. I tried using the temporary solder mask again and it worked great. I guess the first time I did not let the mask to cure long enough. Also, I inquired about have the via's plugged with SR1000 in the future and I was told by our PCB
Electronics Forum | Mon Aug 10 12:58:04 EDT 2020 | SMTA-64386637
We have found Acrylic CC under QFNs is a failure mechanism in thermal cycling. The coating acts as a wedge and causes solder joint cracks. We do not coat QFNs. To enhance reliability we have the vias plugged with solder mask. This eliminates some
Electronics Forum | Thu Oct 01 08:34:50 EDT 2009 | davef
First, the reflow thermal recipe provided by your paste supplier is only a ball park guess. Beyond that, the temperature measured by thermocouples on your oven heaters are only loosely related the temperature of solder paste on your board. You need t
Electronics Forum | Tue Feb 19 11:08:22 EST 2002 | Chris Anglin
Guideline for Tenting Interstitial BGA Vias It is difficult to give a complete recommendation on via tenting without an idea what process conditions are required (ex: wave pass, double reflow, rework etc.). Via Pads (as Test Points) - On Bottom
